1. Field of the Invention
The present invention relates to a semiconductor device including a power source wiring and a ground wiring.
2. Description of the Related Art
In recent years, a technique that reduces unevenness in the potential of electrode pads for a power source or in the potential of electrodes pads for a ground of the semiconductor chip has been utilized. This realizes a semiconductor device with increased electric properties. In such semiconductor device, for example, a power source voltage for the electrode pads for the power source is supplied from a common power source wiring in a package substrate, and a ground voltage for the electrode pads for the ground is supplied from a common ground wiring in the package substrate. This prevents unevenness in potential.
FIG. 1 is a schematic diagram showing a semiconductor chip and its peripherals in semiconductor device related to the present invention. FIG. 2 is a longitudinal sectional view of the semiconductor device shown in FIG. 1. FIG. 3 is a diagram showing a substrate wiring of the semiconductor device viewed from a side of semiconductor chip 201. FIG. 4 is a diagram showing the substrate wiring of the semiconductor device viewed from a side of external terminals 204. FIGS. 3 and 4 show external form 201a of the package.
In an example shown in FIGS. 1 to 4, pad row 220P including electrode pads 220 is formed on both sides of the upper surface of semiconductor chip 201 mounted on circuit board 202 and encapsulated by 205, with the circuit board 202 including conductive vias 203 connected to the external terminals 204 by way of conductive traces 240W.
There exists a plurality of types of power sources and grounds in the semiconductor device. These types of power sources and grounds include a second power source and ground system (VDDQ and VSSQ) for mainly providing a power source potential and a ground potential for a data output circuit, and a first power source and ground system (VDD and VSS) for mainly providing the power source potential and the ground potential for the circuit excluding the data output circuit.
In a configuration of the semiconductor device shown in FIG. 1, first power source pad 220Q1d is included in pad rows 220P on both sides. Likewise, first ground pad 220Q1s is included in pad rows 220P on both sides. That is, the potentials of the first power source and ground system (VDD and VSS) are supplied to a wide area on the semiconductor chip. Thus, pads for the first power source and ground system (VDD pad and VSS pad) on semiconductor chip 201 may be disposed on semiconductor chip 201 in a distributed manner.
On the other hand, second power source pad 220Q2d and second ground pad 220Q2s are disposed adjacent to DQ system signal pads 220QDQ. More specifically, potentials of the second power source and ground system (VDDQ and VSSQ) are supplied adjacent to data input and output pads from the outside to the inside of the semiconductor chip. Thus, the pads for the second power source and ground system (VDDQ pad and VSSQ pad) are disposed adjacent to the data input and output pads (DQ pads) on the semiconductor chip.
Each of the pads and each of the connection lands 230 are connected to each other by bonding wire 206. A wiring runs from each connection land 230.
In the example shown in FIGS. 1 to 4, each pad and each connection land are directly connected by the bonding wire. On the other hand, a configuration where an additional wiring layer of a power source or a ground is provided on a semiconductor chip mounted on a circuit board is disclosed in Japanese Patents Laid-Open Nos. 2004-327757 and 2003-332515. Means disclosed in these documents for routing the power source wiring or the ground wiring using the additional wiring layer provided on the semiconductor chip is useful for reducing impedances of the power source wiring and the ground wiring on the circuit board.
However, if the means disclosed in Japanese Patent Laid-Open No. 2004-327757 or 2003-332515 is used for a semiconductor device mounted with a semiconductor chip such as a DRAM, a problem arises in which speedup of the signal transmission is prevented even though impedances of the power source wiring and the ground wiring on the circuit board are reduced.
Thus, inventors of the present invention have diligently studied this problem, and thereby found that the problem arises due to the following causes.
As described above, the power source and the ground externally supplied with the potential include the first power source and ground system (VDD and VSS) mainly supplying the circuit excluding the data output circuit with the power source potential and the ground potential, and the second power source and ground system (VDDQ and VSSQ) mainly supplying the data output circuit with the power source potential and the ground potential.
Among them, the potential of the first power source and ground system (VDD and VSS) is supplied to a wide area on the semiconductor chip. Thus, the pads for the first power source and ground system (VDD pad and VSS pad) may be disposed on the semiconductor chip in a distributed manner. On the semiconductor chip with the disposition of edge pads in two rows shown in FIG. 1, for example, the pads for the first power source and ground system are disposed in the pad rows on both sides. Thus, as shown in FIGS. 3 and 4, when first power source wiring 240C1d and first ground wiring 240C1s (first power source and ground system) are routed around semiconductor chip 201 on circuit board 202, the following problems arise. For example, when first power source wiring 240C1d is routed as shown in FIG. 5, a problem occurs in which the wire routing involves a long distance. In addition, a problem unavoidable occurs in an area in which the width of the wire decreases, and further, there is an increase in the distance of the wire routing in order to keep the wire separate from each other. Therefore, the method of routing using the additional wiring layer as disclosed in Japanese Patent Laid-Open No. 2004-327757 or 2003-332515 is advantageous to the first power source and ground system because the impedance of the wiring can be reduced.
On the other hand, second power source pad 220Q2d and second ground pad 220Q2, are disposed adjacent to DQ system signal pad 220QDQ. Bonding wires 206 are extended from respective pads so as to run parallel to each other. By thus matching the direction in which bonding wires 206 extended from second power source pad 220Q2d and from second ground pad 220Q2s with matching the direction in which bonding wires 206 are extended from DQ system signal pads 220QDQ, the second power source and ground system forms a feedback current path of the output signal, thereby reducing switching noise owing to switching of the output circuit.
However, if the second power source and ground system wirings are routed on the additional wiring layer formed on the semiconductor chip, the direction in which bonding wires 206 are extended from second power source pad 220Q2d and second ground pad 220Q2s and the direction in which bonding wires 206 are extended from DQ system signal pads 220QDQ become different from each other. As a result, the feedback current path of the output data signal by the second power source and ground system is distorted, and the effect of reducing switching noise decreases. That is, the switching noise increases and speedup of the signal transmission is prevented.